During conventional semiconductor manufacturing processes, unwanted materials are formed on the semiconductor wafer and on features formed on the semiconductor wafer. Usually, these unwanted materials must be removed or etched from the semiconductor wafer. Unfortunately, not all unwanted materials are easily removed or etched from the semiconductor wafer or the features formed on the semiconductor wafer.
With reference now to Prior Art FIG. 1, a cross sectional view illustrating a step associated with a prior art semiconductor device formation method is shown. In a conventional salicidation process, a semiconductor substrate 102 has at least one source diffusion region 104 and at least one drain diffusion region 106 formed therein. A polysilicon gate 108 is disposed between source diffusion region 104 and drain diffusion region 106. In one prior art approach, an oxide etch (i.e. a lightly doped drain (LDD) spacer etch) is used to remove oxide residing above source diffusion region 104 and drain diffusion region 106 of semiconductor substrate 102. The LDD spacer etch also forms sidewall spacers 110a and 110b along the sides of polysilicon gate 108. Unfortunately, conventional process steps contaminate source diffusion region 104, drain diffusion region 106, and the top surface of polysilicon gate 108 such that they are not well suited for the formation of silicided regions therein. (Although an LDD spacer etch is specifically recited as causing contamination during conventional process steps, such contamination also results from various other oxide etch steps stopping on silicon, wherein a subsequent silicidation step will occur such as, for example, a contact etch.)
Referring next to Prior Art FIG. 2, a cross sectional view illustrating deleterious polymer deposition associated with a prior art semiconductor device formation method is shown. As shown in Prior Art FIG. 2, conventional oxide etch steps result in the contamination of source diffusion region 104, drain diffusion region 106, and the top surface of polysilicon gate 108. Such contamination is indicated by areas 200 in source diffusion region 104, areas 202 in drain diffusion region 106, and areas 204 in the top surface of polysilicon gate 108. The contamination results when free CF.sub.x species fluorine or free fluorine radicals from the plasma bombard the silicon of source diffusion region 104, drain diffusion region 106, and the top surface of polysilicon gate 108. As a result of the bombardment, a Teflon-like polymer, C.sub.2 F.sub.4 !.sub.n, (e.g. as represented by areas 200, 202, and 204) is formed at the silicon surface of source diffusion region 104, drain diffusion region 106, and the top surface of polysilicon gate 108. In addition, the kinetic energy imparted by the plasma embeds the carbon-flourine polymer several atomic layers deep into the silicon surface forming a polymer-coated, carbon/fluorine-embedded silicon damage layer.
Referring still to Prior Art FIG. 2, contaminant areas 200, 202, and 204 prevents the formation of a continuous layer of metal over source diffusion region 104, drain diffusion region 106, and the top surface of polysilicon gate 108 during subsequent salicidation process steps. The metal is not in close with silicon, and the polymer creates an effective diffusion barrier preventing the two metals from forming an alloy. Hence, contaminant areas 200, 202, and 204 degrade the characteristics of the silicided regions produced after annealing of the discontinuous metal layer. Although numerous attempts have been made to remove the contaminants using wet chemical etches, dips, and plasma ashes (e.g. a hydrofluoric acid dip/soak, an oxygen plasma ash, a sulfuric acid etch/clean), none of these conventional approaches has proven to be sufficiently reproducible to give an acceptable margin of manufacturability.
Thus, the need has arisen for a method to prepare a semiconductor substrate and a polysilicon gate for subsequent silicide formation.